Contents
Preface iv
About the Authors x
Chapter 1 From Zero to One 1
1.1 The Game Plan 1
1.2 The Art of Managing Complexity 2
1.2.1 Abstraction 2
1.2.2 Discipline 3
1.2.3 The Three -Y’s 4
1.3 The Digital Abstraction 5
1.4 Number Systems 7
1.4.1 Decimal Numbers 7
1.4.2 Binary Numbers 7
1.4.3 Hexadecimal Numbers 9
1.4.4 Bytes， Nibbles， and All That Jazz 11
1.4.5 Binary Addition 12
1.4.6 Signed Binary Numbers 13
1.5 Logic Gates 17
1.5.1 NOT Gate 18
1.5.2 Buffer 18
1.5.3 AND Gate 18
1.5.4 OR Gate 19
1.5.5 Other Two-Input Gates 19
1.5.6 Multiple-Input Gates 19
1.6 Beneath the Digital Abstraction 20
1.6.1 Supply Voltage 20
1.6.2 Logic Levels 20
1.6.3 Noise Margins 21
1.6.4 DC Transfer Characteristics 22
1.6.5 The Static Discipline 22
1.7 CMOS Transistors 24
1.7.1 Semiconductors 25
1.7.2 Diodes 25
1.7.3 Capacitors 26
1.7.4 nMOS and pMOS Transistors 26
1.7.5 CMOS NOT Gate 29
1.7.6 Other CMOS Logic Gates 29
1.7.7 Transmission Gates 31
1.7.8 Pseudo-nMOS Logic 31
1.8 Power Consumption 32
1.9 Summary and a Look Ahead 34
Exercises 36
Interview Questions 50
Chapter 2 Combinational Logic Design 53
2.1 Introduction 53
2.2 Boolean Equations 56
2.2.1 Terminology 56
2.2.2 Sum-of-Products Form 56
2.2.3 Product-of-Sums Form 58
2.3 Boolean Algebra 58
2.3.1 Axioms 59
2.3.2 Theorems of One Variable 59
2.3.3 Theorems of Several Variables 60
2.3.4 The Truth Behind It All 62
2.3.5 Simplifying Equations 63
2.4 From Logic to Gates 64
2.5 Multilevel Combinational Logic 67
2.5.1 Hardware Reduction 68
2.5.2 Bubble Pushing 69
2.6 X’s and Z’s， Oh My 71
2.6.1 Illegal Value: X 71
2.6.2 Floating Value: Z 72
2.7 Karnaugh Maps 73
2.7.1 Circular Thinking 74
2.7.2 Logic Minimization with K-Maps 75
2.7.3 Don’t Cares 79
2.7.4 The Big Picture 80
2.8 Combinational Building Blocks 81
2.8.1 Multiplexers 81
2.8.2 Decoders 84
2.9 Timing 86
2.9.1 Propagation and Contamination Delay 86
2.9.2 Glitches 90
2.10 Summary 93
Exercises 95
Interview Questions 104
Chapter 3 sequential Logic Design 107
3.1 Introduction 107
3.2 Latches and Flip-Flops 107
3.2.1 SR Latch 109
3.2.2 D Latch 111
3.2.3 D FIip-Flop 112
3.2.4 Register 112
3.2.5 Enabled Flip-Flop 113
3.2.6 Resettable Flip-Flop 114
3.2.7 Transistor-Level Latch and Flip-Flop
Designs 114
3.2.8 Putting It All Together 116
3.3 Synchronous Logic Design 117
3.3.1 Some Problematic Circuits 117
3.3.2 Synchronous Sequential Circuits 118
3.3.3 Synchronous and Asynchronous
Circuits 120
3.4 Finite State Machines 121
3.4.1 FSM Design Example 121
3.4.2 State Encodings 127
3.4.3 Moore and Mealy Machines 130
3.4.4 Factoring State Machines 132
3.4.5 Deriving an FSM from a Schematic 135
3.4.6 FSM Review 138
3.5 Timing of Sequential Logic 139
3.5.1 The Dynamic Discipline 140
3.5.2 System Timing 140
3.5.3 Clock Skew 146
3.5.4 Metastability 149
3.5.5 Synchronizers 150
3.5.6 Derivation of Resolution Time 152
3.6 Parallelism 155
3.7 Summary 159
Exercises 160
Int
內容試閱：
Preface
This book is unique in its treatment in that it presents digital logic design from the perspective of computer architecture， starting at the beginning with 1’s and 0’s and leading through to the design of a microprocessor.
We believe that building a microprocessor is a special rite of passage for engineering and computer science students. The inner workings of a processor seem almost magical to the uninitiated yet prove to be straightforward when carefully explained. Digital design in and of itself is a powerful and exciting subject. Assembly language programming unveils the inner language spoken by the processor. Microarchitecture is the link that brings it alltogether.
The first two versions of this increasingly popular text cover the MIPS and ARM architectures. As one of the original Reduced Instruction Set Computing architectures， MIPS is clean and excep- tionally easy to understand and build. MIPS remains an important architecture， as it has inspired many of the subsequent architectures， including RISC-V. The ARM architecture has exploded in popu- larity over the past several decades because of its efficiency and rich
ecosystem. More than 50 billion ARM processors have been shipped， and more than 75% of humans on the planet use products with ARM processors.
Over the past decade， RISC-V has emerged as an increasingly important architecture， both pedagogically and commercially. As the first widely used open-source computer architecture， RISC-V offers the simplicity of MIPS with the flexibility and features of modern processors.
Pedagogically， the learning objectives of the MIPS， ARM， and RISC-V editions are identical. The RISC-V architecture has a number of features， including extendibility and compressed instructions， that con- tribute to its efficiency but add a small amount of complexity. The three microarchitectures are also similar， with MIPS and RISC-V architectures sharing many similarities. We expect to offer MIPS， ARM， and RISC-V editions as long as the market demands.
FEATURES
Side-by-Side Coverage of SystemVerilog and VHDL
Hardware description languages (HDLs) are at the center of modern digital design practices. Unfortunately， designers are evenly split between the two dominant languages， SystemVerilog and VHDL. This book introduces HDLs in Chapter 4 as soon as combinational and sequential logic design has been covered. HDLs are then used in Chapters 5 and 7 to design larger building blocks and entire processors. Nevertheless， Chapter 4 can be skipped and the later chapters are still accessible for courses that choose not to cover HDLs.
This book is unique in its side-by-side presentation of SystemVerilog and VHDL， enabling the reader to learn the two languages. Chapter 4 describes principles that apply to both HDLs， and then provides language- specific syntax and examples in adjacent columns. This side-by-side treatment makes it easy for an instructor to choose either HDL and for the reader to transition from one to the other， either in a class or in professional practice.
RISC-V Architecture and Microarchitecture
Chapters 6 and 7 offer in-depth coverage of the RISC-V architecture and microarchitecture. RISC-V is an ideal architecture because it is a real architecture shipped in an increasing number of commercial products， yet it is streamlined and easy to learn. Moreover， because of its popularity in the commercial and hobbyist worlds， simulation and development tools exist for the RISC-V architecture.
Real-World Perspectives
In addition to the real-world perspective in discussing the RISC-V architecture， Chapter 6 illustrates the architecture of Intel x86 pro- cessors to offer another perspective. Chapter 9 (available as an online supplement) also describes peripherals in the cont
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