Pinaki Mazumder教授是密西根大学安娜堡分校（University of Michigan, Ann Arbor）工学院电气工程与计算机科学系的终身教授，IEEE Fellow和AAAS Fellow。1988年开始，莫泽德教授研究电子设计自动化（EDA），并在密西根大学开设研究生课程VLSI Layout Algorithms（EECS527，超大规模集成电路布局算法），至今已在EDA领域耕耘30余载，共发表100多篇*期刊会议论文，出版4本专著。《超大规模集成电路布线技术》（Handbook of VLSI Routing Techniques： Serial and Parallel Models）乃Mazumder教授的扛鼎之作。聚焦超大规模集成电路布线技术，主要研究迷宫布线算法、总体布线算法、详细布线算法（即通道布线与开关盒布线算法等）和特殊布线算法，重点讨论了大量的工业界实用的特殊类型布线与*并行布线器。《超大规模集成电路布线技术》注重基础，从串行与并行布线模型开始，到各种基本布线算法，兼顾芯片设计中的特定情况，针对具体的布线技术，每一章都精心设计案例研究（ca
PREFACE
This handbook for routing interconnects inside a VLSI chip provides mathematical models of important classes of wiring techniques for students interested in gaining insights in integrated circuits layout automation techniques and for practicing engineers working in the field of electronic design automation EDA. This book presents a comprehensive review on VLSI routing techniques that was undertaken in early 1990s with a view to developing a generalized routing accelerator that could speed up routing chores for different styles of wiring techniques, namely, maze routing used widely for connecting different circuit blocks by finding the shortest path, channel routing used in connecting standard cells of uniform heights and variable widths arranged in the form of rows of cells, switchbox routing used in connecting surrounding multiple blocks of dissimilar aspect ratios within an enclosed routing area, and so on.
In 1988, when I started my academic career at the University of Michigan, I designed a new graduatelevel course on computeraided design, EECS 527： VLSI Layout Algorithms. The course was introduced to educate graduate students and spur doctoral research in thethen burgeoning field of computeraided design CAD for integrated circuits ICs that propelled the exponential growth of integration density in VLSI chips, as postulated by Moores Law. At that time, there was no suitable textbook on the subject to teach graduate students about the stateoftheart layout algorithms that were key to design complex VLSI chips. Therefore, I combed through the literature on the subject and assembled the course materials in order to teach students systematically basic underlying mathematical techniques for circuit partitioning, floorplanning, cell placement, and routing. Subsequently, I engaged my own doctoral students to expand my lecture materials in the form of comprehensive reviews.
For example, with the assistance of my doctoral student, Dr. K. Shahookar, who studied the Genetic Algorithm GA for VLSI cell placement techniques, I coauthored a 78page review paper, which was published in ACM Computing Surveys in June 1991. After poring over nearly a hundred publications on placement algorithms for standard cells and macrocells, I divided them into five main categories： i the placement by simulated annealing, ii the forcedirected placement, iii the placement by mincut graph algorithms, iv the placement by numerical optimization, and v the evolutionbased placement. While the first two types of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. The taxonomy of placement algorithms was created to study inherent parallelism of the different classes of algorithms. While designing the course, I realized that in order to push the mammoth potential of Moores Law, the chip design phase must be accelerated several folds by harnessing the evolving computing platforms.
In the late 80s, the computing platforms for the VLSI design environment were rapidly transforming from midframe computers, namely, Digital Equipment Corporation Vax 11780, Hewlett Packard HP 3000, and Wang Laboratories Wang VS, to the network of workstations, what is widely known as the NOW. This opportunity in hardware evolution warranted deeper insights into VLSI cell placement and routing P&R techniques so that sequential algorithms that used to run on standalone midframe computers could be rendered into parallel CAD algorithms for running efficiently on the NOW platform. Also, emergence of commercial parallel computers such as Intel hypercube and Sequent Computer System shared memory had further pushed the needs for developing parallel P&R algorithms.
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